The present invention relates to a semiconductor memory. More particularly, the present invention pertains to a semiconductor memory designed to achieve reduction in the cell area of a static random-access MOS memory and large immunity against soft errors induced by alpha particles.
A typical conventional flip-flop type static memory cell comprises two highly resistive loads and four n-channel MOS transistors, as described, for example, in Japanese Pat. Laid-Open No. 72069/1980. More specifically, as shown in FIG. 1, which is an equivalent circuit diagram, the drain of each of the pair of driver MOS transistors T.sub.1 and T.sub.2 is connected to the gate of the other of the two, and load resistors R.sub.1 and R.sub.2 are connected to the respective drains of the transistors. The sources of the transistors T.sub.1 and T.sub.2 are fixed to a predetermined voltage (e.g., a ground voltage), and a lower supply voltage Vcc is applied to the other ends of the resistors R.sub.1 and R.sub.2, thus supplying a very small current to a flip-flop circuit consisting of the transistors T.sub.1, T.sub.2 and the resistors R.sub.1, R.sub.2. Further, transfer MOS transistors T.sub.3 and T.sub.4 are respectively connected to storage nodes N.sub.1 and N.sub.2 of this flip-flop circuit. The above-described four transistors T.sub.1, T.sub.2, T.sub.3, T.sub.4 and two load resistors R.sub.1, R.sub.2 constitute in combination a memory cell for one bit. It should be noted that the reference numeral 1 denotes a word line, and 2a, 2b denote data lines. The load resistors R.sub.1 and R.sub.2 are generally formed using highly resistive polycrystalline silicon.
The related prior art will be described hereinunder in detail with reference to FIGS. 2, 3A and 3B. FIG. 2 shows a cross-sectional structure corresponding to the prior art shown in FIG. 1. Referring to FIG. 2, gate electrodes 1a and 1c of MOS transistors provided over a region 16 which is provided on a substrate 26 are formed from a first-level conductive layer, and a highly resistive load is formed from a highly resistive region 7e which is formed in a part of polycrystalline silicon that defines a second-level conductive layer. Low-resistive polycrystalline silicon regions 7b and 7c are provided at both ends, respectively, of the highly resistive region 7e, the silicon region 7c serving as a wiring for the power supply voltage Vcc, and the silicon region 7b being connected to a source diffusion region 3d of a transfer MOS transistor.
Diffusion regions 3b, 3d and 3f are used as sources or drains of the MO transistors.
The reference numerals 8, 9, 10 and 11 denote insulator films. The numeral 2b denotes a data line, and 4b a contact portion of the data line 2b.
FIGS. 3A and 3B show a planar layout of an arrangement for one bit, in which: FIG. 3A shows a layout of transfer MOS transistors and driver MOS transistors; and FIG. 3B shows a layout of highly resistive polycrystalline silicon. Referring to FIG. 3A, the word line la defines a common gate for the transfer MOS transistors T.sub.3 and T.sub.4. Data lines 2a and 2b formed from, for example, aluminum electrodes, are connected to the drain diffusion regions 3a and 3b of the MOS transistors T.sub.3 and T.sub.4 through contact holes 4a and 4b respectively. The gate electrodes 1b and 1c of the driver MOS transistors T.sub.1 and T.sub.2 are directly connected to the sources 3c and 3d of the MOS transistors T.sub.3 and T.sub.4 through contact holes 5a and 5b, respectively. The respective sources of the driver MOS transistors T.sub.1 and T.sub.2 are interconnected through a heavily-doped n-type diffusion layer (n.sup.+ -layer) 3f. The n.sup.+ -layer 3f is used to supply the ground voltage Vss to the sources of all the driver MOS transistors in the memory. As shown in FIG. 3B, the low-resistive polycrystalline silicon 7c is used to supply the power supply voltage Vcc to all the highly resistive loads in the memory.
In the figures, the reference numeral 5c denotes a contact hole for connecting together the diffusion layer and the gate electrode, 3e the drain diffusion region of the MOS transistor T.sub.2, 6a, 6b contact holes for connecting together the diffusion layer or the gate electrode and second-level polycrystalline silicon, 7a, 7b, 7c second-level polycrystalline silicon regions, R.sub.1, R.sub.2 load resistances, and 7d, 7e highly resistive regions.
We have found that static memory cells having the above-described conventional structure suffer from the following problems:
(1) The n.sup.+ -layer 3f which is employed as a wiring for supplying the ground voltage to the sources of the driver MOS transistors causes an increase in the longitudinal dimension of the memory. Further, the n.sup.+ -layer 3f involves the problem that, when the memory is in an operative state, for example, a current flows to the driver MOS transistor T.sub.1 from the data line 2a through the transfer MOS transistor T.sub.3 in the arrangement shown in FIG. 1, and at this time, a voltage drop occurs between memory cells since the n.sup.+ -layer has a relatively high sheet resistance, i.e., 20 to 100 .OMEGA./.quadrature.. In order to solve this problem, it has heretofore been necessary to provide one aluminum wiring per several cells and supply the ground voltage to the n.sup.+ -layer through these aluminum wirings, which means that the aluminum wirings lead to an increase in the overall area of the memory chip.
(2) Very small amounts of uranium (U) and thorium (Th) are contained in a ceramic or resin material used to seal and package memory chips and also in a wiring material. The penetration of an alpha particle emitted by the decay of uranium and thorium atoms causes the generation of an electron-hole pair along the path of the particle. If one of the electron-hole pair is mixed into the charge stored at the storage nodes N.sub.1, N.sub.2, the potential at the nodes N.sub.1, N.sub.2 is undesirably changed, so that the storage information in the memory fails. This is a phenomenon known as "soft error". In conventional static memories, an amount of charge which is sufficient to compensate for a charge loss due to alpha particles can be stored by means of the P-N junction capacitance defined between the n.sup.+ -diffusion layer constituting the drain regions of the driver MOS transistors T.sub.1, T.sub.2 and the p-type silicon substrate and the insulator film capacitance provided by the gate oxide film. However, as the memory cell area is reduced, it is impossible to store an amount of charge which is sufficient to compensate for a loss due to alpha particles. Accordingly, the conventional static memory structure involves the problem that miniaturization leads to an increase in the soft error rate and results in a considerable lowering in the reliability of the memory.
(3) Conductive characteristics of highly resistive polycrystalline silicon employed to form load resistors are determined by the potential barrier which is formed at the grain boundary. Accordingly, when a film which has a large amount of charge captured therein, such as a plasma nitride film, is employed as a protective film for a memory cell or when an electrode material such as an aluminum wiring is formed, the height of the potential barrier at the grain boundary in the highly resistive polycrystalline silicon may be changed, resulting in the resistance value of the load resistors being varied.
(4) Formation of a contact hole that connects together a data line and a transfer MOS transistor has a need in layout to ensure a margin for possible error in mask alignment between the contact hole and the gate electrode of the transfer MOS transistor, and this causes an increase in the longitudinal dimension of the memory cell, which makes it difficult to reduce the memory cell area.